Subtopic Notes

15.1 Processors, Parallel Processing and Virtual Machines

15. Hardware and Virtual Machines

RISC (Reduced Instruction Set Computer)

A processor design that uses a small set of simple instructions that execute very quickly

CISC (Complex Instruction Set Computer)

A processor design that uses a larger set of complex instructions, some of which can perform multiple operations in a single instruction

RISCCISC
Reduced Instruction Set ComputerComplex Instruction Set Computer
Simpler InstructionComplex Instructions
Less number of instructionHigher number of instructions
Fixed-length instructionsVariable-length instructions
Fewer range of instruction formatWide range of instruction format
Most instructions complete in a single clock cycleInstructions often require multiple clock cycles
Uses multiple registers for operationsFewer general-purpose registers
Hardwired control (faster and simpler)Microprogrammed control (more flexible)
Well-suited for efficient pipeliningComplex instructions make pipelining harder
Limited number of addressing modesRich set of addressing modes
Only LOAD and STORE instructions access memoryMany instructions can directly access memory
Less power RequiredUses more power
Cheaper to manufactureMore expensive
Uses more memory in spaceTakes up less space in memory
Eg. ARM (Smart phone processors), Apple M1/M2/M3Eg. Intel x86 (e.g., Core i5, i7, i9), AMD Ryzen
Used in high-end applications such as video processing, telecommunications and image processing.Used in low-end applications such as security systems, home automations, etc.
  • A program written for a RISC processor cannot run on a CISC processor, and vice versa.
  • Even programs written for one RISC processor may not run on another RISC processor, as their instruction sets can differ.

Interrupt handling on CISC and RISC

  • When an interrupt is detected, the current processes are paused and their state is saved in registers.
  • The Interrupt Service Routine (ISR) is loaded into the pipeline and executed.
  • After the ISR completes, the paused processes are resumed by restoring their state from the registers back into the pipeline.
  • Both architectures strive to respond to interrupts promptly and resume execution correctly, though they approach it with different design philosophies

CISCRISC
More complex and slower because instructions vary in length and complexity, requiring more steps to save/restore stateSimple and fast due to uniform, fixed-length instructions and fewer addressing modes.
Might include hardware support to automatically save and restore the processor stateRestoring processor state is usually managed by software
Frequently includes specialized instruction for interrupt handlingDepends on software routines to handle interrupt
Faster processSlower
Less FlexibleMore predictable

Pipelining

  • Technique where multiple instruction phases are overlapped, allowing the CPU to work on several instructions simultaneously
  • Form of instruction-level parallelism
  • Pipelining in CISC: Harder to pipeline because of variable-length, complex instructions and multi-cycle operations.
  • Advantages
    • Makes RISC processors more efficient due to simple, fixed-length instructions
    • Reduces idle time for processor components.
    • Better use of CPU components
  • Disadvantage
    • Interrupt handling: There are some instructions in the pipeline so during an interrupt, the processor needs to remove previous instructions and then handle the interrupt.

Typical pipelining in RISC includes the following steps

  • Instruction Fetch (IF): Fetch the instruction from memory.
  • Instruction Decode (ID): Decode the instruction and identify required operands.
  • Operand Fetch (OF) / Memory Access (MEM): Access the operands from registers or memory.
  • Instruction Execution (IE / EX): Perform the operation (ALU computation, branch, etc.).
  • Result Write Back (WB): Write the result back to the register file.

Example of pipelining

  • Let’s say we have four instructions (A, B, C, D) to process using pipelining.
  • Each instruction passes through five stages: IF → ID → OF → IE → WB.
  • Pipelining allows overlap: while instruction A moves to the next stage, instruction B starts its fetch, instruction C waits for the previous stage, and so on.
  • After the pipeline is fully filled, one instruction completes every clock cycle, increasing throughput.
  • This is the main advantage of pipelining: even though each instruction still takes 5 cycles, multiple instructions are processed simultaneously, reducing total execution time.
Stage
Time Interval
1
2
3
4
5
6
7
8
Instruction Fetch (IF)
A
B
C
D
Instruction Decode (ID)
A
B
C
D
Operand Fetch (OF)
A
B
C
D
Instruction Execution (IE)
A
B
C
D
Result Write Back (WB)
A
B
C
D

Number of instructions = 4
Number of stages in the pipeline = 5
Without Pipelining it will require: 4 instructions × 5 cycles = 20 cycles
Using pipelining total cycles
= Pipeline stages + (Number of instructions − 1) = 5 + ( 4 - 1 ) = 8 cycles
Number of cycle saved = 20 - 8 = 12

Use of registers in pipelining

  • Registers are fast, temporary storage locations inside the CPU
  • RISC processors make extensive use of registers to store operands instead of frequently accessing RAM
  • Intermediate values are kept in registers between instruction stages.
  • Using registers helps reduce memory bottlenecks, allowing pipelining to operate efficiently

Four basic computer architecture

  • Computer architecture refers to the design and organization of a computer system.
  • It specifies how the system fetches, processes, and stores data and instructions.
  • It defines how components such as the CPU, memory, and input/output devices collaborate to execute programs.
  • Categorized based on
    • Single or multiple instruction streams
    • Single or multiple data streams

SISD (Single Instruction, Single Data)

  • Executes one instruction on one data stream at a time
  • Found in early computers
  • Contains a single processor → no pipelining
  • Simple architecture, sequential execution
  • Eg. Classic desktop CPU running one task at a time

SIMD (Single Instruction Multiple Data)

  • Executes the same instruction on multiple data elements simultaneously
  • Found in array processors and vector processors
  • Useful for parallel processing
  • Contains multiple processors, each with its own memory
  • Efficient for tasks like matrix operations, graphics, and scientific computing
  • Eg. GPU operations, image processing

MISD (Multiple Instruction Single Data)

  • Executes multiple instructions on the same data stream.
  • Rarely used; sometimes for fault-tolerant systems or sorting large data sets.
  • Contains multiple processors processing the same data
  • Eg. Redundant systems in safety-critical environments

.
MIMD (Multiple Instruction Multiple Data)

  • Executes different instructions on different data streams simultaneously.
  • Each processor works independently on its own instruction/data.
  • Efficient for parallel processing and multitasking.
  • Eg. Multi-core CPUs, distributed systems, cloud computing

Massively Parallel Computers

  • Systems with thousands of processors working together on a single large problem
  • Each processor executes part of a program; results are combined for the final output
  • Used in scientific research, weather simulation, cryptography, AI
  • Processors may have shared or separate memory and communicate via high-speed links
  • Data and task parallelism allow many operations or different tasks to run simultaneously
  • Special software distributes work efficiently, and processors work as a tightly coupled system
  • SIMD applies one instruction to many data points, while MIMD runs different instructions on different data

Virtual Machine

  • Allows a process to interact with a software interface provided by the OS, effectively creating a replica of the hardware.
  • The OS kernel manages communication with the actual host hardware

AdvantagesDisadvantages
Enables running multiple operating systems on the same system.Performance is lower compared to running a native OS.
Supports multiple instances of the same OS.Implementation requires time and effort.
Allows experimental or development work to be done without riskParticular hardware may be difficult to emulate
Provides a safe environment for testing without causing real-world damageUsing virtual machine means execution of extra code

Examples:

  • Companies use VMs to run legacy software on newer hardware
  • Server consolidation: Multiple virtual servers run on a single physical machine
  • Developers can test applications across different systems without needing to buy extra hardware
  • Users can run emulators for gaming or mobile apps on PCs (Example Bluestacks)